The USB 3.0 functional layer
Technical Bulletin: USB 3.1 | DesignWare IP | Synopsys
USB 2.0 PHY Verification
Technical Bulletin: USB 3.1 | DesignWare IP | Synopsys
Figure 7 from The USB 2.0 Physical Layer: Standard and Implementation | Semantic Scholar
Solved Host End Device Human Layer Human Layer Application | Chegg.com
1/8 Port USB 3.0 Switch - Quarch Technology
USB PHYISICAL LAYER PROTOCOL ENGINE LAYER APPLICATION LAYER - ppt download
USB 2.0 PHY IP core | Arasan Chip Systems
Protocol in Depth - USB - Read more on SemiWiki
USB Link Layer Protocol - ppt video online download
Physical Layer Explained!!. The physical layer is aimed at… | by Rakesh Elamaran | Coinmonks | Medium
VLSI IMPLEMENTATION OF PHYSICAL LAYER CODING USED IN SUPER SPEED USB USING VERILOG | Semantic Scholar
USB (Communications) - Wikipedia
The USB 3.0 functional layer
The new kid on the USBlock: introducing SuperSpeed 3.0 - Tech Design Forum Techniques
USB 3.2 with xHCI & Retimer Verification IP | Truechip
File:Wireless USB protocol stack.png - Wikimedia Commons
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Truechip
How to design the USB circuitry
Figure 2 from Implementation of USB 3.0 SuperSpeed physical layer using Verilog HDL | Semantic Scholar
USB 3.0 protocol layer - part 1
